The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, wafer-level chip scale package structures have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In a wafer-level chip scale package structure, active devices such as transistors and the like are formed at the top surface of a substrate of the wafer-level chip scale package structure. A variety of metallization layers comprising interconnect structures are formed over the substrate. A metal pad is formed over the top metallization layer and electrically coupled to the interconnect structures. A passivation layer and a first polymer layer may be formed over the metal pad. The metal pad is exposed through the openings in the passivation layer and the first polymer layer.
A first seed layer is then formed on the first polymer layer. Post-passivation interconnect (PPI) metal lines and pads may be formed over the first seed layer by using suitable fabrication techniques such as forming and patterning a first photo resist layer on the first seed layer, plating the PPI metal lines and pads in the openings in the first photo resist layer, and then removing the first photo resist layer. Furthermore, the portions of the first seed layer that were previously covered by the first photo resist layer are removed by using suitable etching processes.
A second polymer layer may be formed over the PPI lines and pads. A second opening for an under bump metallization (UBM) structure is formed by using suitable fabrication techniques such as patterning. A second seed layer is formed over the second polymer layer. The UBM structure is formed extending into the second opening in the second polymer layer, wherein the UBM structure is electrically connected to the PPI metal lines and pads. The fabrication steps of the UBM structure include forming a second photo resist layer over the second seed layer, patterning the second photo resist layer, forming the UBM structure on the second seed layer, removing the second photo resist layer, and removing the portions of the second seed layer that were previously covered by the second photo resist layer.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.